The present disclosure relates generally to designing a circuit for inclusion in a semiconductor device and, more particularly, to optimizing circuit performance using via pillars.
The process of manufacturing integrated circuits (ICs) include several stages, of which, the definition of a pattern associated with the circuit is of critical importance. The pattern may be generated during the design process, and in particular in a layout design. The pattern may then be fabricated on a substrate using photolithography processes.
There is significant pressure on the semiconductor industry to enable smaller and smaller critical dimensions of integrated circuits. At the same time, increased performance, in terms of lower power and/or faster timing capabilities, are desired as well. As critical dimensions of integrated circuits decrease, including widths of circuit paths between circuit elements, the resistance of such circuit paths increases, leading to potential problems such as increased power consumption and/or slower performance.
In designing integrated circuits, routing of interconnections between circuit elements can have a drastic effect on performance. In particular, as circuit features decrease in size, such routing can represent a not insignificant source of signal delay. In one particular example, resistance experienced at vias between conductive layers can increase delay in signal propagation between circuit elements; such resistance becomes more significant at smaller sizes and higher performance levels (lower voltage, higher frequence) that are increasingly desired.
Accordingly, improvements in design and layout of integrated circuits that improve timing of circuit layouts are desired.